Advanced packaging stands out as a major highlight in the ‘More than Moore’ era. As chip miniaturization becomes increasingly challenging and costly at each process node, engineers are opting to place multiple chips into advanced packaging rather than struggle to further shrink the chips.

3D packaging

In 2.5D packaging, bare die stacks or side-by-side placements rest atop an interposer with silicon vias (TSVs). The base, or the interposer, provides connectivity between chips. In 3D IC packaging, logic die stacks together or with memory die stacks without constructing a large System on Chip (SoC). Connections between bare dies occur through an active interposer, while in 2.5D IC packaging, components are stacked on the interposer using conductive bumps or TSVs. On the other hand, 3D IC packaging connects multiple layers of silicon wafers using TSV-enabled components.

Chiplet packaging

A series of modular chips in a chip library can be integrated into packaging using die-to-die interconnect technology. Chiplets represent another form of 3D IC packaging, enabling the heterogeneous integration of CMOS and non-CMOS components. In essence, they are smaller System on Chips (SoCs) or chiplets rather than large SoCs in the package. Breaking down large SoCs into smaller chips boasts higher yields and lower costs compared to a single bare die. Chiplets empower designers to leverage various IPs without concern for process nodes or manufacturing technologies. They can use diverse materials, including silicon, glass, and laminates, in chip fabrication.

Fan-out (FO) packaging

In FO packaging, connections fan out across the chip surface, providing more external I/O. It embeds bare dies entirely in epoxy molding compound (EMC), eliminating process flows like wafer bumps, underfill, flip chips, cleaning, underfill spraying, and curing, thus bypassing the need for an interposer, simplifying heterogeneous integration. Compared to other packaging types, FO technology offers smaller packages with more I/O. In 2016, it enabled Apple to integrate TSMC’s packaging technology, housing its 16nm application processor and mobile DRAM into one package for the iPhone 7, becoming a technological standout.

Fan-out wafer-level packaging (FOWLP)

This technology is an enhancement of wafer-level packaging (WLP), offering more external connections for silicon chips. It embeds chips into EMC, constructs a high-density redistribution layer (RDL) on the wafer surface, and applies solder balls, forming a reconstituted wafer. Typically, treated wafers are first cut into individual bare dies, then dispersed on a carrier structure, and the gaps are filled to form a reconstituted wafer. FOWLP provides numerous connections between the package and the application circuit board, and due to the larger substrate than bare dies, the spacing between the dies is, in fact, more lenient.